The present invention relates to an automatic frequency control circuit and, more particularly, to an automatic frequency control circuit of a horizontal sync signal for television or the like.
In a conventional technique, an automatic frequency control circuit for a horizontal sync signal of a television signal and an even/odd filed discriminating circuit in a scanning frame are respectively constituted by independent circuits.
In a conventional automatic frequency control circuit 3, as shown in FIG. 3, a phase-locked loop (PLL) phase-locked to a horizontal sync signal input IH is constituted by a phase comparator 31, a low-pass filter (LPF) 32, and a voltage-controlled oscillator (VCO) 33 having the same frequency as a horizontal sync signal frequency.
An operation of a conventional automatic frequency control circuit will be described below.
FIGS. 4A to 4E are timing charts showing the operation of the conventional automatic frequency control circuit 3.
An output x (FIG. 4B) from the VCO 33 locked to the horizontal input signal IH (FIG. 4A) is delayed by a delay circuit 34 constituted by a resistor and a capacitor to obtain a signal e (FIG. 4C), and the signal e is inverted by an inverter 35 to generate a delayed signal f (FIG. 4D). The logical NOR between the delayed signal f and the output x from the voltage-controlled oscillator 33 is calculated by an NAND gate 36 so as to generate a horizontal sync signal output OH (FIG. 4E).
As described above, when noise is mixed in an input signal in a weak electric field or the like or a signal is omitted, this signal is corrected to output a stable signal.
A conventional even/odd field discriminating circuit 4, as shown in FIG. 5, is constituted by a counter 41, a decoder 42, flip-flops 43 and 44, and a discriminator 45.
An operation of the conventional even/odd field discriminating circuit 4 will be described below.
FIGS. 6A to 6G are timing charts showing the operation of the circuit shown in FIG. 5.
In this circuit, two input timing signals for a vertical sync signal V (FIG. 6B) are generated by a counter 41 for counting the number of clocks CK from the ON timing of a horizontal sync signal output H, an output from a decoder 42 for the count value, a timing T1 (FIG. 6C) phase-locked to the horizontal sync signal (FIG. 6A), and a timing T2 (FIG. 6D) shifted by a half period of the timing T1.
A phase relationship between the horizontal sync signal H and the vertical sync signal V is determined by the discriminator 45 in an order of vertical timing signals g and h (FIGS. 6E and 6F) derived from the vertical sync signal V latched by the flip-flops 43 and 44 at the timings T1 and T2, and the discriminator 45 outputs a discrimination output (FIG. 6G) for determining whether a field generated by the vertical sync signal is an even field or an odd field.
For example, when a scanning field is an even field, a phase relationship between the horizontal sync signal H and the vertical sync signal V becomes a relationship represented by a solid line in FIG. 6B, and the vertical sync signal V is input in an order of the timings T1 and T2. Therefore, the vertical timing signals g and h are output in an order named.
In contrast to this, when a scanning field is an odd field, a relationship between the horizontal sync signal H and the vertical sync signal V becomes a relationship represented by a dotted line in FIG. 6B, and the vertical sync signal V is input in an order of the timings T2 and T1. Therefore, the vertical timing signals h and g are output in an order named.
The discriminator 45 determines the value of a discrimination output F in an order of the vertical timing signals g and h.
Since the above conventional automatic frequency control circuit is independent of an even/odd field discriminating circuit in a scanning frame, high-precision clocks for generating timing signals for supplying a vertical sync signal to the even/odd field discriminating circuit, a counter for counting the number of clocks, and a decoder for extracting the timing signals from the count value of the counter are disadvantageously required.
The automatic frequency control circuit requires a delay circuit, constituted by a resistor and a capacitor, for generating a horizontal sync signal output having a duty ratio of about 7.4% from an output having a duty ratio of 50% from the VCO of the PLL. However, when the resistor and capacitor are incorporated in a semiconductor integrated circuit, the duty ratio is disadvantageously changed due to a large area occupied by the resistor and capacitor, a change in power source voltage, and ununiformity of elements.